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Integrated Circuit Systems, Inc.
ICS85301
2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER
FEATURES
* 2:1 LVPECL MUX * 1 LVPECL output * 2 differential clock inputs can accept: LVPECL, LVDS, CML * Maximum input/output frequency: 3GHz * Translates LVCMOS/LVTTL input signals to LVPECL levels by using a resistor bias network on nPCLK0, nPCLK0 * Propagation delay: 490ps (maximum) * Part-to-part skew: 150ps (maximum) * Additive phase jitter, RMS: 0.009ps (typical) * Full 3.3V or 2.5V operating supply * Lead-Free package fully RoHS compliant * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS85301 is a high performance 2:1 Differential-to-LVPECL Multiplexer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS85301 can also perform differential translation because the differential inputs accept LVPECL, CML as well as LVDS levels. The ICS85301 is packaged in a small 3mm x 3mm 16 VFQFN package, making it ideal for use on space constrained boards.
ICS
BLOCK DIAGRAM
PCLK0 nPCLK0 PCLK1 nPCLK1
PIN ASSIGNMENT
0
Q nQ PCLK0 1 nPCLK0 2 PCLK1 3 nPCLK1 4 5
VBB
16 15 14 13 12 11 10 9 6
CLK_SEL
VCC
VEE
VEE
nc
VEE Q nQ VEE
1
7
nc
8
VCC
CLK_SEL V BB
ICS85301
16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View
PCLK0 nPCLK0 PCLK1 nPCLK1 VBB CLK_SEL nc VCC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 nc VEE VEE VCC VEE Q nQ VEE
ICS85301
16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View
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REV. A MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS85301
2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Type Description Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Bias voltage. No connect. Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When LOW, selects PCLK0, nPCLK0 inputs. LVCMOS / LVTTL interface levels. Positive supply pins. Negative supply pins. Differential output pair. LVPECL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 7, 16 6 8, 13 9, 12, 14, 15 10, 11 Name PCLK0 nPCLK0 PCLK1 nPCLK1 VBB nc CLK_SEL VCC VEE nQ, Q Input Input Input Input Output Unused Input Power Power Output Pulldown Pulldown Pullup/ Pulldown Pulldown Pullup/ Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 1 37 37 Maximum Units pF k k
TABLE 3. CONTROL INPUT FUNCTION TABLE
Input CLK_SEL 0 1 Input Selected PCLK PCLK0, nPCLK0 PCLK1, nPCLK1
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REV. A MAY 23, 2005
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ICS85301
2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER
4.6V -0.5V to VCC + 0.5 V 50mA 100mA 51.5C/W (0 lfpm) 89C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA 16 VFQFN 16 TSSOP Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5%, TA = -40C TO 85C
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 26 Units V mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V 5%, TA = -40C TO 85C
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 2.5 Maximum 2.625 24 Units V mA
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V 5% OR 2.5V 5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK_SEL CLK_SEL CLK_SEL CLK_SEL VCC = VIN = 3.465V or 2.625V VCC = 3.465V or 2.625V, VIN = 0V -150 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 Units V V A A
NOTE: Outputs terminated with 50 to VCC/2. See Parameter Measurement Information, "Output Load Test Circuit".
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5%, TA = -40C TO 85C
Symbol Parameter IIH IIL VPP VCMR VOH VOL VBB Input High Current Input Low Current PCLK0, nPCLK0, PCLK1, nPCLK1 PCLK0, PCLK1 nPCLK0, nPCLK1 Test Conditions VCC = VIN = 3.465 VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -10 -150 150 1.2 2.01 1.24 1.695 1200 3.3 2.535 1.845 2.145 Minimum Typical Maximum 150 Units A A A mV V V V V
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Output High Voltage; NOTE 3 Output Low Voltage; NOTE 3 Bias Voltage
NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V. NOTE 3: Outputs terminated with 50 to VCC - 2V. .
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2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Test Conditions PCLK0, nPCLK0, PCLK1, nPCLK1 PCLK0, PCLK1 nPCLK0, nPCLK1 VCC = VIN = 2.625V VCC = 2.625V, VIN = 0V VCC = 2.625V, VIN = 0V -10 -150 150 1.2 1.25 0.48 0.935 1200 2.5 1.705 1.005 1.305 Minimum Typical Maximum 150 Units A A A mV V V V V
TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = 2.5V 5%, TA = -40C TO 85C
Symbol Parameter Input High IIH Current IIL VPP VCMR VOH VOL VBB Input Low Current
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Output High Voltage; NOTE 3 Output Low Voltage; NOTE 3 Bias Voltage
NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V. NOTE 3: Outputs terminated with 50 to VCC - 2V. .
TABLE 5A. AC CHARACTERISTICS, VCC = 3.3V5%, TA = -40C TO 85C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Par t-to-Par t Skew; NOTE 2, 3 Input Skew Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time Output Duty Cycle MUX Isolation f = 622MHz 622MHz (Integration Range: 12KHz - 20MHz) 20% to 80% 240 Test Conditions Minimum Typical Maximum 3 490 150 25 0.009 100 48 -55 200 52 Units GHz ps ps ps ps ps % dBm
tsk(pp) tsk(i) tjit
tR / tF odc MUX_ISOL
All parameters measured at f 1.7GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VCC = 2.5V5%, TA = -40C TO 85C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Par t-to-Par t Skew; NOTE 2, 3 Input Skew Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time Output Duty Cycle MUX Isolation f = 622MHz 622MHz (Integration Range: 12KHz - 20MHz) 20% to 80% 240 Test Conditions Minimum Typical Maximum 3 490 150 25 0.009 100 47 -55 200 53 Units GHz ps ps ps ps ps % dBm
tsk(pp) tsk(i) tjit
tR / tF odc MUX_ISOL
For notes, see Table 5A above.
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REV. A MAY 23, 2005
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ICS85301
2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in
0 -10 -20 -30 -40 -50
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter
3.3V or 2.5V @ 622MHz (12KHz to 20MHz) = 0.009ps typical
SSB PHASE NOISE dBc/HZ
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
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REV. A MAY 23, 2005
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ICS85301
2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
2V
2V
VCC
Qx
SCOPE
VCC
Qx
SCOPE
LVPECL
nQx
LVPECL
nQx
VEE
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
VCC nQx nPCLK0, nPCLK1 PART 1 Q0x
V
nPCLK0, nPCLK1
PP
Cross Points
V
nQy PART 2 Qy
CMR
tsk(pp)
V EE
DIFFERENTIAL INPUT LEVEL
PART-TO-PART SKEW
nQ nPCLK0, nPCLK1 PCLK0, PCLK1 nQ Q
tPD
Q
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
PROPAGATION DELAY
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2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER
nPCLK0
80%
PCLK0 nPCLK1 PCLK1 nQ Q
tPD2 tPD1 tsk(i)
80% VOD
Clock Outputs
20% tR tF
20%
tsk(i) = |tPD1 - tPD2|
INPUT SKEW
OUTPUT RISE/FALL TIME
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REV. A MAY 23, 2005
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ICS85301
2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS
Figure 1A shows an example of the differential input that can be wired to accept single ended LVCMOS levels. The reference voltage level VBB generated from the device is connected to
the negative input. The C1 capacitor should be located as close as possible to the input pin.
VCC
R1 1K Single Ended Clock Input
PCLK
V_REF
nPCLK
C1 0.1u
R2 1K
FIGURE 1A. SINGLE ENDED LVCMOS SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS
Figure 1B shows an example of the differential input that can be wired to accept single ended LVPECL levels. The reference
voltage level VBB generated from the device is connected to the negative input.
VCC(or VDD)
CLK_IN
PCLK VBB nPCLK
FIGURE 1B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
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drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to
Zo = 50
3.3V 125 125
FOUT
FIN
Zo = 50
Zo = 50
FOUT
50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
RTT =
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
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2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER
ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
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REV. A MAY 23, 2005
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2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER
here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK R2 50
3.3V Zo = 50 Ohm
3.3V
R1 100 Zo = 50 Ohm
PCLK nPCLK HiPerClockS PCLK/nPCLK
CML Built-In Pullup
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 R2 84 HiPerClockS Input
R5 100 - 200 R6 100 - 200 R1 50 R2 50 Zo = 50 Ohm C2 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 PCLK VBB nPCLK PC L K /n PC L K
R4 125
FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V 3.3V 2.5V R3 120 SSTL Zo = 60 Ohm PCLK Zo = 60 Ohm nPCLK HiPerClockS PCLK/nPCLK R4 120
3.3V 3.3V Zo = 50 Ohm LVDS R5 100 Zo = 50 Ohm R1 1K R2 1K C1 PCLK C2 VBB nPCLK PC L K /n PC L K
R1 120
R2 120
FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
FIGURE 4F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
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decoupling capacitor should be located as close as possible to the power pin.
APPLICATION SCHEMATIC EXAMPLE
Figure 5 shows an example of ICS85401 application schematic. This device can accept different types of input signal. In this example, the input is driven by a LVDS driver. The
3.3V C1 0.1u 3.3V Zo = 50 R2 100 Zo = 50 LVDS 1 2 3 4 CLK0 nCLK0 CLK1 nCLK1 16 15 14 13 nc GND GND VDD
nc CLK_SEL nc VDD
GND Q nQ GND
12 11 10 9
Zo = 50 + R1 Zo = 50 100 -
3.3V Zo = 50 R3 100 Zo = 50 LVDS
U1 ICS85401
3.3V
R4 1K
5 6 7 8
C2 0.1u
FIGURE 5. ICS85401 APPLICATION SCHEMATIC EXAMPLE
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REV. A MAY 23, 2005
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ICS85301
2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85301. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS85301 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 26mA = 90.09mW Power (outputs)MAX = 27.83mW/Loaded Output pair
Total Power_MAX (3.465, with all outputs switching) = 90.09mW + 27.83mW = 117.92mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 0 linear feet per minute and a multi-layer board, the appropriate value is 51.5C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.118W * 51.5C/W = 91.1C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE JA
FOR
16-PIN VFQFN, FORCED CONVECTION
JA at 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 51.5C/W
TABLE 6B. THERMAL RESISTANCE JA
FOR FOR
16 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W
200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
ICS85301
2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT
RL
50 VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V
OH_MAX
=V
CC_MAX
- 1.005V
(VCC_MAX - VOH_MAX) = 1.005 * For logic low, VOUT = V (V
CC_MAX
OL_MAX
=V
CC_MAX
- 1.78V
-V
OL_MAX
) = 1.78V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V
OH_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 1.005V)/50] * 1.005V = 20mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.78V)/50] * 1.78V = 7.83mW Total Power Dissipation per output pair = Pd_H + Pd_L = 27.83mW
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REV. A MAY 23, 2005
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2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER RELIABILITY INFORMATION
TABLE 7A. JAVS. AIR FLOW TABLE
FOR
16 LEAD VFQFN
JA at 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 51.5C/W
TABLE 7B. JAVS. AIR FLOW TABLE
FOR
16 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W
200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85301 is: 137
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2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER
16 LEAD VFQFN
PACKAGE OUTLINE - K SUFFIX
FOR
TABLE 8A. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A3 b e ND NE D D2 E E2 L 0.25 0.30 0.25 3.0 1.25 0.50 0.18 0.50 BASIC 4 4 3.0 1.25 0.80 0 0.25 Reference 0.30 MINIMUM 16 1.0 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
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16 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8B. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 8 0.10 Millimeters Minimum 16 1.20 0.15 1.05 0.30 0.20 5.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
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2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Marking 301A 301A 01AL 01AL 85301AG 85301AG TBD TBD Package 16 Lead VFQFN 16 Lead VFQFN 16 Lead "Lead-Free" VFQFN 16 Lead "Lead-Free" VFQFN 16 Lead TSSOP 16 Lead TSSOP 16 Lead "Lead-Free" TSSOP 16 Lead "Lead-Free" TSSOP Shipping Packaging Tray 2500 Tape & Reel Tray 2500 Tape & Reel tube 2500 tape & reel Tube 2500 Tape & Reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS85301AK ICS85301AKT ICS85301AKLF ICS85301AKLFT ICS85301AG ICS85301AGT ICS85301AGLF ICS85301AGLFT
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85301AK
www.icst.com/products/hiperclocks.html
18
REV. A MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS85301
2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER
REVISION HISTORY SHEET Description of Change Ordering Information Table - corrected count. Added 16 Lead TSSOP package throughout the datasheet. Date 11/17/04 5/23/05
Rev A A
Table T9
Page 17
85301AK
www.icst.com/products/hiperclocks.html
19
REV. A MAY 23, 2005

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